Department
Computer Science and Cybersecurity
Document Type
Poster
Abstract
Modern processors use multi-level cache hierarchies to reduce memory access delays but selecting an effective replacement policy remains challenging because program access patterns vary and hardware has strict constraints. Recent peer-reviewed studies examine several approaches, including rule-based designs, adaptive policies that adjust to workload behavior, and lightweight learning-based methods. These techniques improve miss rate, energy efficiency, and overall performance, often outperforming traditional LRU methods when access patterns change rapidly. In modern mobile and embedded processors, such improvements lead to better responsiveness and lower power consumption. Overall, this review highlights how current research builds on core cache concepts while addressing trade-offs between implementation complexity and performance gains.
Publication Date
Spring 4-9-2026
Recommended Citation
Gebretsadik, R. (2026, April 9). Performance and efficiency of cache replacement policies in multi-level memory hierarchies variability [Poster presentation]. Student Research Conference Spring 2026, Saint Paul, MN, United States. https://metroworks.metrostate.edu/student-scholarship/39
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-No Derivative Works 4.0 International License.
Comments
Spring 2026: Student Research Conference